SiFive
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SiFive
- 1875 South Grant Street Suite 600, San Mateo, CA 94402
- https://www.sifive.com
- info@sifive.com
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buildroot
Forked from buildroot/buildrootBuildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
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Kami
Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bluespec. It is actually a complete rewrite of an older version from MIT
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freedom-tools
Tools for SiFive's Freedom Platform
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freedom-e-sdk
Open Source Software for Developing on the Freedom E Platform
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sifive-blocks
Common RTL blocks used in SiFive's projects
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api-chisel3-sifive
Wake build description for chisel3
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api-firrtl-sifive
Wake build description for firrtl
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devicetree-overlay-generator
Generates Devicetree overlays which encode the assumptions and/or sane defaults
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ProcKami
Kami based processor implementations and specifications
hardware coq riscv hardware-designs formal-verification riscv-simulator -
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StdLibKami
Standard Library of Kami Modules
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wit
Workspace Integration Tool
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riscv-llvm
SiFive's LLVM working tree
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freedom-metal
Bare Metal Compatibility Library for the Freedom Platform
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freedom-u540-c000-bootloader
Freedom U540-C000 Bootloader Code
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freedom-devicetree-tools
A linker script generator for SiFive's Freedom platform
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trace-decoder
SiFive implementation of the Nexus Trace decoder
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RiscvSpecFormal
The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.
hardware coq riscv hardware-designs formal-verification riscv-simulator -
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wake
The SiFive wake build tool
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api-generator-sifive
Wake build descriptions of hardware generators
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